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this is preliminary information on a new product now in dev elopment or undergoing evaluati on. details are subject to change without notice. december 2015 docid028766 rev 1 1/24 stch02 offline pwm controller for ultra-low standby adapters datasheet - preliminary data features ? advanced power management for ultra-low standby power consumptions (under 10 mw at 230 vac) ? fully integrated primary side constant current output regulation (cc) ? 650 v embedded hv start-up circuit with zero power consumption. ? quasi resonant (qr) ze ro voltage switching (zvs) operation ? automatic self-supply ? accurate and adjustable output ovp with autorestart after fault ? input voltage feedforward compensation for mains-independent cc regulation ? intelligent frequency jit ter for emi suppression ? so-8 package applications ? ac-dc chargers for smartphones, tablets, camcorders and other handheld equipment ? ac/dc adapters for stb, notebooks and auxiliary power supplies description the stch02 is a pwm quasi resonant controller specifically designed for ultra-low standby power supplies. the built-in hv startup cell with zero power consumption, the fully integrated blocks for primary side constant current output regulation and the advanced power management make this ic the best choice to build a high efficiency and ultra-low standby consumption power supply, with high overall and excellent dynamic performances. figure 1. typical application so-8 table 1. device summary order code package packing stch02 so-8 tube STCH02TR tube and reel (% 7%% (/% 4&/4& ;$% '# /$ )7 45$) 7p vu (/% "$*/ "$*/ ". www.st.com
contents stch02 2/24 docid028766 rev 1 contents 1 device description and block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 frequency jittering for emi reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 high voltage start-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 zero current detection and triggering block . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 constant voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 constant current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 voltage feedforward block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 burst mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9 adaptive uvlo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11 soft-start and starter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.12 hiccup mode ocp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 so-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
docid028766 rev 1 3/24 stch02 device description and block diagram 24 1 device description and block diagram the stch02 is a current mode controller designed for offline quasi resonant zvs (zero voltage switching at switch turn-on) flyback converters. it combines a high performance low voltage pwm controller chip and a 650 v hv start-up cell in the same package. the device features a unique characteristic: it is capable to provide a constant output current (cc) regulation using primary-sensin g feedback. this eliminates the need for a dedicated current refe rence ic, as well as the current sensor, still maintaining a quite accurate output current regulation. the quasi resonant operation is achieved by means of a transformer demagnetization sensing input that triggers mosf et's turn-on, connected on th e zcd pin. this input serves also to monitor the output voltage monitor and to achieve the mains independent cc regulation (line voltage feedforward). the maximum switching frequency is top-limited below 260 khz, so that at the medium- light-load a special function au tomatically lowers the operat ing frequency still maintaining the operation as close to zvs as possible. at the very light-load, the device enters a controlled burst mode operation that, along with the zero power high voltage start-up circuit, the extremely low quiescent current of the device, helps minimize the residual input consumption, thus meeting the requirements of the most stringent standards. during the cc regulation, wher e the flyback volta ge generated by th e auxiliary winding drops and may be not enough to supply the internal circuits, the chip is able to power itself directly from the rectified mains through the high voltage start-up circuit. during the burst mode operation the self-supply fe ature is disabled (due to very stringent no load consumption requirement), and the v dd supply voltage has to be guaranteed by proper application design. in any case, an innovative adaptive uvlo he lps minimize the issues related to the fluctuations of the self-supply voltage with the output load, due to transformer's parasitic and further reducing the ic's bias consumption. in addition to the said functions that optimize power handling under different operating conditions, the device offers also a protection against the transformer saturation and secondary diode short-circuit and an adjustable output overvoltage protection. all of them are in the autorestart mode. an embedded leading edge blanking on the current sense input for greater noise immunity completes the equipment of this device.
device description and block diagram stch02 4/24 docid028766 rev 1 figure 2. block diagram ;$% 071 -0(*$ 071 (% 3'' 7p d q 4&/4& %sjw fs *g g '# 4611-: boe67-0 )7@0/ *tubsuvq 67-0 )7 7%% sfgfsfodfwpmubhft *oufsobmtvqqmzcvt boe 'ffegpsxbse -0(*$ *g g $$ $7 -&# 4 3 2 563/0/ -0(*$ 45"35&3 (/% 071 4 3 2 18. #-0$, *sfg 3 4 2 4boe) %&."( -0(*$ #-"/,*/( ".
docid028766 rev 1 5/24 stch02 device description and block diagram 24 figure 3. pin connection (top view) table 2. thermal data symbol parameter max. value unit r th j-amb thermal resistance, junction to ambient 150 c table 3. absolute maximum ratings symbol pin parameter value unit v hv 1 voltage range (referred to gnd) -0.3 to 650 v i hv 1 output current self limited ma 3 to 6 analog inputs and outputs -0.3 to 3.6 v i zcd 4 zero current detector current 3 ma i gd 7 output totem pole peak current self limited v dd 8 supply voltage (i cc < 25 ma) self limited v i dd 8 device supply current + internal zener capability 25 ma t j junction temperature range -40 to 150 c t stg storage temperature -55 to 150 c table 4. pin functions no. name function 1hv high voltage start-up. the pin, able to withst and 650 v, is to be tied directly to the rectified mains voltage. when the voltage on the pin reaches the hv start voltage (50 v typ.) a 7 ma internal current source charges the capacitor connected between v dd and gnd to start-up the ic. when the voltage on the v dd pin reaches the turn- on threshold (13 v typ.) t he generator is shut down and re-enabled as the v dd voltage falls below the turn-off threshold ( 10 v typ.). in this way, if the auxiliary winding is not delivering sufficient voltage or it is not used at all, the ic keeps on running. this feature is disabled in case a protection is tripped, and the generator is restarted after v dd has dropped below v ddr (4.5 v typ.) 2nc not internally connected. a provision fo r clearance on the pcb to meet safety requirements. )7 7%% /$ ;$% $0.1 (% (/% 4&/4& ".
device description and block diagram stch02 6/24 docid028766 rev 1 3fb control input for duty cycle control. a voltage set 65 mv below the threshold v fbb activates the burst mode operation. a level close to the threshold v fbl means that we are approaching the cycle-by-cycle overcurrent setpoint. 4zcd transformer's demagnetization sensin g for the quasi resonant operation and input/output voltage monitor. a negative-goi ng edge triggers the mosfet's turn-on. the current sourced by the pin during mosfet's on-time is monitored to get an image of the input voltage to the converter, in order to compensate the internal delay of the current sensing circuit and achiev e a cc regulation independent of the mains voltage. still, the pin voltage is sampled- and-held right at the end of transformer's demagnetization to get an accurate image of the output voltage to be used for overvoltage protection (ovp). please note that the maximum izcd sunk/sourced current has to not exceed 3 ma (amr ) in the entire input voltage range. no capacitor is allowed between the pin and the auxiliary winding of the transformer. 5 sense input to the pwm comparators. the current flowing in the mosfet is sensed through a resistor connected between the pin and gnd. the resulting voltage is compared with an internal reference (0.75 v max.) to determine the mosfet's turn- off. the pin is equipped with 380 ns blanki ng time after the gate drive output goes high for improved noise immunity. if a second comparison level located at 1 v is exceeded the ic is stopped and restarted after v dd has dropped below v ddr (4.5 v typ.). 6gnd circuit ground reference and current return for both - the signal part of the ic and the gate drive. all of the grou nd connections of the bias components should be tied to the trace going to this pin and kept separate from any pulsed current return. 7 gd a gate driver with a totem pole output stage for the external power mosfet. 8vdd supply voltage of the device. an electrolytic capacitor, connected between this pin and ground, is initially charged by the inte rnal high voltage start-up generator. when the device is running the same generator w ill keep it charged in case the voltage supplied by the auxiliary winding is not suffic ient. this feature is disabled in case a protection is tripped. sometimes a small bypass capacitor (0.1 f typ.) connected between the pin and gnd might be useful to get a clean bias voltage for the signal part of the ic. table 4. pin functions (continued) no. name function
docid028766 rev 1 7/24 stch02 device description and block diagram 24 table 5. electrical characteristics (tj = - 25 to 125 c, v dd = 14 v, unless otherwise specified) symbol parameter test condition min. typ. max. unit high voltage start-up generator v hv hv voltage i hv < 2 a, tj = 25 c 650 v i leakage hv leakage current v hv = 400 v, tj = 25 c 1 a h vstart hv start voltage 40 50 60 v i charge v dd start-up charge current v hv > hv start; v dd ? 0.6 v or after protection tripping 0.3 0.6 0.9 ma v hv > hv start ; 2 < v dd < v ddon 4.5 7 10.3 v dd-fold v dd foldback threshold v hv > hv start 12v supply voltage v dd operating range after turn-on 11.5 23 v v dd-on turn-on threshold 12 13 14 v v dd-off restart threshold v fb > v fbf 91011v v dd-uvlo uvlo threshold v fb > v fbf 8.55 9.5 10.45 v v fb < (0.6 - 65 mv) 6.75 7.5 8.25 v v ddr v dd restart voltage (falling) after protection tripping 4.5 v in burst mode 3.2 v z v z clamping voltage i dd = 20 ma 23 26.5 v supply current i q quiescent current burs t operation 190 230 a i dd operating supply current c out = 1 nf, f sw = 100 khz 2.3 2.7 ma i dd-fault fault quiescent current during hiccup 330 420 a start-up timer and frequency limit t start start timer period 220 s f lim internal frequency limit 260 khz zero current detector i zcdb input bias current v zcd = 0.1 to 2.7 v 1 a v zcdh upper clamp voltage i zcd = 1 ma 3 v v zcdl lower clamp voltage i zcd = - 1 ma -60 mv v zcda arming voltage positive-going edge 80 110 140 mv v zcdt triggering voltage negative-going edge 40 60 80 mv t blank trigger blanking time after mosfet's turn-on v fb ?? 1.65 v 3.8 s v fb = 0.6 v 24
device description and block diagram stch02 8/24 docid028766 rev 1 t d-on turn-on delay time after triggering v gate = 6 v, c gate = 1 nf 270 ns t force force turn-on time after blanking 10 14 s gate driver v gdl output high voltage v dd = 8.5 v; i gate = 5 ma 7 v i gate = 5 ma 10.5 13 t rise rising time c gate = 1 nf 70 110 150 ns t fall falling time c gate = 1 nf 20 40 60 ns v gdl output low voltage i gd-sink = 50 ma 1 v line feedforward r ff equivalent feedforward resistor i zcd = 1 ma 63 70 77 ? feedback input v fbh upper saturation 3.45 v h fb current sense gain 3.22 3.29 3.36 i fb feedback source current 70 100 130 a v fbb burst mode threshold voltage falling 0.54 0.6 0.66 v v fbf exit burst mode thre shold 0.64 0.72 0.8 v v hyst burst mode hysteresis 50 65 75 mv current reference v refx maximum value internal, not measured 0.8 v k i current loop gain 0.19 0.2 0.21 v overvoltage protection v ovp ovp threshold 2.375 2.5 2.625 v n ovp consecutive cycles for ovp triggering v ovp = 2.5 v 4 current sense t leb leading edge blanking v gate = 6 v, c out = 1 nf 270 380 490 ns t d gate delay to output v gate = 6 v, c out = 1 nf 150 ns v csx max. clamp value dv cs /dt = 200 mv/s 0.7 0.75 0.8 v v ocp hiccup mode ocp level 0.95 1 1.05 v v sense_bm minimum burst mode sense voltage 72 mv table 5. electrical characteristics (tj = - 25 to 125 c, v dd = 14 v, unless otherwise specified) (continued) symbol parameter test condition min. typ. max. unit
docid028766 rev 1 9/24 stch02 device description and block diagram 24 frequency jittering f d modulation frequency 9 khz v zcdh modulation duty cycle 50 % ? ipk peak current change 5 % table 5. electrical characteristics (tj = - 25 to 125 c, v dd = 14 v, unless otherwise specified) (continued) symbol parameter test condition min. typ. max. unit
typical circuit stch02 10/24 docid028766 rev 1 2 typical circuit figure 4. typical configuration $ 3 $ $ $ 3&' 3 3 3 3 3 7 '# 4&/4& 7%% $633&/5 $0/530- (/% ;$% )7 (% 45$) % #3 3 % % "$*/ "$*/ (/% 7pvu . 3 3 $ $ 3 3 ".
docid028766 rev 1 11/24 stch02 application information 24 3 application information the stch02 is an offline cc mode primary sens ing switching controller, specific for offline quasi resonant zvs (zero voltage switching at switch turn-on) flyback converters. depending on converter's load condition, the device is able to work in different modes (see figure 5 ): 1. qr mode at the heavy load. quasi resonan t operation lies in sy nchronizing mosfet's turn-on to the transformer's demagnetizatio n by detecting the resulting negative-going edge of the voltage across any winding of the transformer. then the system works close to the boundary between discontin uous (dcm) and continuous conduction (ccm) of the transformer. as a result, the switching frequency will be different for different line/load conditions (see the hy perbolic-like portion of the curves in figure 5 ). minimum turn-on losses, low emi emission a nd safe behavior in the short-circuit are the main benefits of this kind of operation. 2. valley-skipping mode at the medium/light-l oad. depending on voltage on the fb pin, the device defines the maximu m operating frequency of the converter. as the load is reduced mosfet's turn-on will not any more occur on the first valley but on the second one, the third one an d so on. in this way the sw itching frequency will no longer increase. 3. burst mode with no or a very light-load. when the load is extremely light or disconnected, the converter will enter a controlled on/o ff operation with the constant peak current. decreasin g the load will then result in fr equency reduction, which can go down even to few hundred hertz, thus mini mizing all frequency related losses and making it easier to comply with energy saving regulations or recommendations. being the peak current very low, no issue of audible noise arises. figure 5. multi-mode operation of stch02 g tx 1jonby *oqvu wpmubhf 1 jo g ptd #vstunpef 7bmmfztljqqjoh npef 2vbtjsftpobou npef ".
application information stch02 12/24 docid028766 rev 1 3.1 gate driver the gate driver of the power mosfet is designe d to supply a controlled gate current during both turn-on and turn-off in order to minimize the common mode emi. under uvlo conditions an internal pull-down circuit holds the gate low in order to ensure that the power mosfet cannot be turned on accidentally. 3.2 frequency jitterin g for emi reduction although the stch02 device works in the qr mode and the switching frequency is already modulated at twice of the mains frequency , dedicated frequency jittering circuitry is embedded inside the ic to further reduce the emi filtering. a proprietary frequency jitter technique is implemented in the controller, ba sed on the injection of a modulating signal at 9 khz (above the feedback loop bandwidth) with 50% duty cycle on the current sense signal: this signal is a square waveform that modulates the amplitude of the peak primary current. the percentage of this amplitude is set as a default at 5%. as the peak current reduces with decreasing load levels, the effect of this modulation automatically attenuates at lower loads, where the energy of emi noise is highly reduced. 3.3 high voltage start-up generator based on a 650 v rated depletion mosfet embedded into the startup cell, the hv current generator is supplied through the drain pin and is enabled only if the voltage on the hv pin is higher than the hvstart threshold (50 v typical value). with reference to the timing diagram in figure 6 , when the power is applied to the circuit and the voltage on the input bulk capacitor is hi gh enough, the hv generator is sufficiently biased to start operating, thus it will draw the current i charge (7 ma typ. value) through the hv pin and will charge the capa citor connected between the v dd pin and ground. this charging current will be redu ced at 0.6 ma in case the voltage on the v dd is lower than v dd-fold , in order to prevent exceeding ic dissipation when the pin is accidentally shorted to ground or during a restart after protection triggering. as the v dd voltage reaches the start-up threshold (13 v typ.) the chip starts operating and the control logic disable s the hv generator. while the generator is off, there are virtually no losses across the hv startup cell, except a few hundreds na of the leakage current through the depletion mosfet. the ic is powered by the energy stored in the v dd capacitor until the self-supply circuit (typically an auxiliary winding of the transformer an d a steering diode) develops a voltage high enough to sustain the operation. the chip is able to power itself directly from the rectified ma ins: when the voltage on the v dd pin falls below v dd-off (10 v typ.), the hv current generat or is turned on and charges the supply capacitor until it reaches the v dd-on threshold. in this way, the self-supply circuit develops a vo ltage high enough to sustain the operation of the device. this feature is useful especially during the cc regulation, when the flyback voltage generated by the auxiliary winding alone may not be able to keep v dd within the operative range.
docid028766 rev 1 13/24 stch02 application information 24 at converter power-down the sy stem will the lose the regulation as soon as the input voltage falls below hv start . this prevents converter's restart attempts and ensures monotonic output voltage decay at system power-down. figure 6. timing diagram: normal power-up and power-down sequences 3.4 zero current detection and triggering block the zero current detection (zcd) and triggering blocks switch on the power mosfet if a negative-going edge falling below 50 mv is app lied to the zcd pin. to do so, the triggering block must be previously armed by a positive-going edge exceeding 100 mv. this feature is used to detect transformer de magnetization for the qr operation, where the signal for the zcd input is obtained from the transformer's auxiliary winding used also to supply the ic. the triggering block is blanked after the mosfet's turn-off to prevent any negative-going edge that follows leakage inductance demagn etization from triggering the zcd circuit erroneously. this blanking time is dependent on the voltage on the fb pin: it is t blank = 24 s for v fb = 0.6 v, and decreases linearly down to t blank = 3.8 s for v fb ? 1.65 v. the voltage on the pin is both top and bottom limited by a double clamp. the upper clamp is typically located at 3 v, while the lower clamp is located at -60 mv. the interface between the pin and the auxiliary winding will be a resistor divider. its resistance ratio as well as the individual resistance values will be properly chosen (see section 3.10: overvoltage protection on page 18 and section 3.7: voltage feedforward block on page 16 . 7 */ 7 %% 7 %4 * $)"3(& n" 7 %%0/ )7 45"35 u u u u 7 %%0/ 7 %%67-0 n" ".
application information stch02 14/24 docid028766 rev 1 please note that the maximum izcd sunk/sourced current has to not exceed 3 ma (amr) in all the vin range conditions (88 - 265 vac). no capacitor is allowed between the zcd pin and the auxiliary winding of the transformer. the switching frequency is top-limited below 260 khz, as the converter's operating frequency tends to increase excessively at the light-load and high input voltage. a starter block is also used to start-up the system when the signal on the zcd pin is not high enough to trigger the mosfet after the first few cycles initiat ed by the starter, as the voltage developed across the auxiliary winding becomes large enough to arm the zcd circuit, mosf et's turn-on will start to be locked to transformer demagnetization, hence setting up the qr operation. the starter is activated also when the ic is in the cc regulation and the output voltage is not high enough to allow the zcd triggering. if the demagnetization completes - hence a negative-going edge appears on the zcd pin - after a time exceeding time t blank from the previous turn-on, the mosfet will be turned on again, with some delay to ensure minimum voltage at turn-on. if, instead, the negative- going edge appears before t blank has elapsed, it will be ignored and only the first negative-going edge after t blank will turn-on the mosfet. in th is way one or more drain ringing cycles will be skippe d (?valley-skipping mode?, figure 7 ) and the switching frequency will be prevented from exceeding 1/t blank . figure 7. drain ringing cycle skipping as the load is progressively reduced when the system operates in the valley-skip ping mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the off-time of the mosfet is allowed to change with discre te steps of one ringing cycle, while the off-time needed for cycle-by-cycle energy balance may fall in betw een. thus one or more longer switching cycles will be compensated by one or more shorter cycles and vice versa. however, this mechanism is absolutely normal and there is no appreciable effect on the performance of the converter or on its output voltage. 1jo1johh1joh 1jo1johhh1johh u 5 04$ u 7 %4 u 1jo1johh1joh 5 04$ 5 04$ 7 %4 7 %4 ".
docid028766 rev 1 15/24 stch02 application information 24 3.5 constant voltage operation the device is specific for secondary feedback. the fb pin is connected to an optocoupler which transmits the error signal from the regulation loop located on the secondary side of the converter. typically, a ts431 is used as a voltage reference. the fb pin is driven directly by the phototran sistor's collector to mo dulate the duty cycle. the voltage coming from the fb pin is compared with the voltage across the sense resistor, controlling the peak drai n current cycle-by-cycle. figure 8. voltage control principle: internal schematic 3.6 constant current operation the voltage of the auxiliary wind ing is fed into the internal cc block trough the zcd pin to achieve an output constant current regulation. equation 1 can be used to define to output current in cc mode. equation 1 this formula shows that the average output current does not depend anymore on the input or the output voltage, neither on transformer inductance values. the external parameters defining the output current are the tran sformer ratio and the sense resistor r sense . the current loop gain k i is internally defined (see table 5 on page 7 ). 'spn3tfotf *g c $g c 5p 18.mphjd 3g c $7 7g c '# ". s e n s e i s e c p r i o u t r 2 k n n i ? ? ?
application information stch02 16/24 docid028766 rev 1 3.7 voltage feedforward block the current control structure uses the voltage v c to define the output current, according to equation 1 . actually, the cc comparator will be affected by an internal propagation delay td, which will switch off the mosfet with a p eak current than high er the foreseen value. the stch02 device implements a line feedforward function, which solves the issue by introducing an input voltage dependent offset on the current sense signal, in order to adjust the cycle-by-cycle current limitation. the external schematic configuration is shown in figure 9 . figure 9. feedforward compensation: internal schematic the r zcd resistor can be calculated as follows: equation 2 where r ff is an internal parameter, defined in table 5 on page 7 . in this case the peak drain current does not depend on input voltage anymore. ". 3g c "vy 3[de 3tfotf 7 '# 4&/4& 7%% $633&/5 $0/530- (/% ;$% )7 (% 45$) s e n s e d f f p r p r i a u x z c d r t r l n n r ? ? ? ?
docid028766 rev 1 17/24 stch02 application information 24 3.8 burst mode operation when the voltage at the fb pin falls down 65 mv below than v fbb , the burst mode operation starts: the mosfet is turned off in order to reduce the consumption. after the mosfet turn off, the fb pin voltage, as resu lt of the feedback reaction to the energy delivery stop, increa ses up to the v fbb and the device restarts the switch again. during these switching cycles the ma x. peak current is fixed (about v sense_bm /r sense ) by an internal clamp inside the current limit circuit. the effect of the burst mode operation is to reduce the equivalent switching frequency, which can go down even to few hundred hertz, minimizing all frequency related losses and maki ng it easier to comply with energy saving regulations. this kind of operation, shown in the timing diagrams of figure 10 along with the other ones, is audible noise free sinc e the peak current is low. figure 10. adaptive minimum restart time: timing diagrams * %4 7 '## 7 '# u u n7 iztufs #vstunpef /psnbmnpef /psnbmnpef 7 '#' 7 %%67-0 7 7 u ".
application information stch02 18/24 docid028766 rev 1 3.9 adaptive uvlo a major problem when optimizing a converter fo r minimum no load consumption is that the voltage generated by the auxilia ry winding under these conditi ons falls considerably as compared even to a few ma load. this very often causes the supply voltage vdd of the control ic to drop and, as th e self-supply is disabled during the burst mode, it can go below the uvlo threshold so that the operation becomes intermittent, which is undesired. furthermore, this must be traded off agains t the need of generating a voltage not exceeding the maximum allowed by the control ic at the full load but low enough to reduce the bias losses as much as possible. to help the designer to overcome this problem, the device besides reducing its own consumption during the burst mode operation, also features a proprietary adaptive uvlo function. it consists of shifting the v dd-uvlo threshold downwards at the light-load, namely when the voltage at the fb pin falls 65 mv below the burst mode threshold v fbb (0.6 v typ.), to have more headroom. to prevent any malfunction the normal thres hold (9.5 v typ.) is re-established when the voltage at the fb pin exceeds the exit burst mode threshold v fbf . the normal uvlo threshold ensu res that at full me dium-heavy loads the mosfet will be driven with a proper gate to source voltage. the mode of operation is reported in figure 10 . 3.10 overvoltage protection the overvoltage function of the stch02 device monitors the voltage on the zcd pin during mosfet's off-time, where t he voltage generated by the auxiliary winding tracks converter's output voltage. if the voltage applied to the pin exceeds an internal 2.5 v reference, a comparator is triggered, an over voltage condition is assumed and the device is shut down. once r zcd is fixed by feedforward considerations (see section 3.7: voltage feedforward block ) it is possible to calculate the value of the r ovp resistor to activate the ovp protection for a certain output voltage level, v out-ovp : equation 3 where v ovp is the internal ovp threshold, n sec and n aux are the secondary and auxiliary turn's number respectively. to reduce sensitivity to noise and prevent the latch from being erroneously activated, the ovp comparator must be triggered for four co nsecutive oscillator cy cles before the stch02 device is stopped. a counter, which is reset every time the ovp comparator is not triggered in one oscillator cycle, is provided to this purpose. figure 11 illustrates the timing of the function.
docid028766 rev 1 19/24 stch02 application information 24 once the protection is tripped, th e condition is maintained until v dd goes below v ddr restart voltage. while it is disabled, however, no energy is coming from the self-supply circuit; and the voltage on the v dd capacitor will drop down to v ddr restart voltage, before the v dd capacitor is charged again and the device restarted (v dd-on ). ultimately, this will result into a low frequency intermittent operation (hiccup mode operation). figure 11. ovp function: timing diagram 3.11 soft-start and starter block the soft start feature is automatically implemented by the constant current block, as the primary peak current will be li mited from the voltage on the internal cc block capacitor. during the start-up, as the output voltage is zero, the ic will start in the cc mode with no high peak current operations. in this way the voltage on the output capacitor will increase slowly and the soft-start feature will be ensured. 3.12 hiccup mode ocp the device is also protected against the short-ci rcuit of the secondary rectifier, short-circuit on the secondary winding or a hard-saturated flyback transformer. a comparator monitors continuously the voltage on the r sense and activates protection circuitry if this voltage exceeds the v ocp value (1 v typ. value). to distinguish an actual malfunction from a di sturbance (e.g.: induced during esd tests), the first time the comparator is tripped the protec tion circuit enters a ?warning state?. if in the subsequent switching cycle the comparator is not tripped, a tempor ary disturbance is assumed and the protection logic will be reset in its idle state; if the co mparator will be tripped again a real malf unction is assumed and th e device will be stopped. once the protection is tripped, th e condition is maintained until v dd goes below v ddr restart voltage. while it is disabled, however, no energy is coming from the self-supply circuit; hence the voltage on the v dd capacitor will decay and cross th e uvlo threshold after some 7bvy 7 u u u $06/5&3 3&4&5 u $06/5&3 45"564 u ;$% 071 '"6-5 /03."-01&3"5*0/ 5&.103"3:%*4563#"/$& '&&%#"$,-001'"*-63& u ".
application information stch02 20/24 docid028766 rev 1 time, which clears the latch. the internal start-up genera tor is still off, then the v dd voltage still needs to go below its re start voltage before the v dd capacitor is charged again and the device restarted. ultimately, th is will result in a low frequenc y intermittent operation (hiccup mode operation), with very low stress on t he power circuit. this special condition is illustrated in the timing diagram of figure 12 . figure 12. hiccup mode ocp: timing diagram 7 %4 4fdpoebszejpefjttipsufeifsf u u u 7 4063$& 5xptxjudijohdzdmft 7 %% 7 %%0/ 7 %%0'' 7 %%3 7 0$1 ".
docid028766 rev 1 21/24 stch02 package information 24 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 4.1 so-8 package information figure 13. so-8 package outline
package information stch02 22/24 docid028766 rev 1 table 6. so-8 package mechanical data symbol dimensions mm inch min. typ. max. min. typ. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d (1) 1. dimension d does not include mold flash, protrusions or gate burrs. mold flash, p r otrusions or gate burrs shall not exceed 0.15 mm (0.006 inch) in total (both sides). 4.80 5.00 0.189 0.197 e 3.80 4.00 0.15 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 k 0 (min.), 8 (max.) ddd 0.10 0.004
docid028766 rev 1 23/24 stch02 revision history 24 5 revision history table 7. document revision history date revision changes 15-dec-2015 1 initial release.
stch02 24/24 docid028766 rev 1 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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